Semiconductor integrated circuits have had their integration density increased by efforts to microfabricate transistor devices which make up the semiconductor integrated circuits. Semiconductor integrated devices on single chips have begun incorporating multifunctionality. Semiconductor memory devices have also had their storage capacity increased regardless of their types, such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), because of microfabricated transistor devices.
In recent years, there have been demands for the development of new technologies for further increasing integration density to achieve multifunctionality and large storage capacity. The first reason for this is that semiconductor chips are more required to have multifunctionality and large storage capacity than transistor devices that are microfabricated to increase multifunctionality and storage capacity, and the second reason is that there are limitations on efforts to microfabricate transistor devices.
One of such new technologies is a layered semiconductor device comprising a plurality of semiconductor chips, which is known as a so-called three-dimensional semiconductor. For example, Patent document 1 discloses an example wherein a memory circuit is integrated in a separate chip stacked on a semiconductor integrated circuit itself, thereby realizing a large-scale integrated circuit without changing the chip area by layering semiconductor chips. Similarly, Patent document 2 discloses a multilayer memory structure comprising memory cell arrays disposed in multiple layers for large storage capacity, thereby realizing a large-scale integrated circuit without changing the size of chip area.
A plurality of semiconductor chips disposed in multiple layers require interconnections between the chips in addition to interconnections in the chips. The interconnections between the chips are mostly in the form connections produced by wire bonding. If wire bonding is applied to layered semiconductors, then wires are bonded to interconnect pads on the surfaces of the chips. However, the wire bonding approach poses some problems. First, the number of wires that can be used is limited because each pad requires a certain pad area of 100 μm squared, for example. Secondly, pads on the surfaces of semiconductor chips need to be mounted on the outer sides of the layered chips so that the pads can be connected from outside of the chips. If identically shaped semiconductor chips are layered, then the bonding wire pads may not be made available.
Generally, two data transmission technologies have been developed to solve the above problems.
The first technology is about through-hole interconnections extending through a semiconductor chip. According to the report from Takahashi, et al (Non-patent document 1), a silicon chip is thinned to 50 μm, and holes of 10 μm squared are formed in the silicon chip. The holes are then filled with metal, providing through-hole interconnections for interconnecting chips. The through-hole interconnections allow interchip interconnections to be arranged in a two-dimensional pattern in the chip plane, making it possible to employ several hundreds interchip interconnections. In addition, since interchip interconnections extend through the chip, it is possible to layer identically shaped semiconductor chips.
The second technology is concerned with the transmission of data between a plurality of semiconductor chips based on the contactless interface technology. The contactless interface technology is roughly classified into a capacitive coupling transmission technology and an inductive coupling transmission technology which employs an inductor. For example, the report from Kanda, et al (Non-patent document 2) introduces a system and a circuit for transmitting data through capacitive couplings. Specifically, pads are provided on a plurality of semiconductor chips at intervals of 40 μm, and the semiconductor chips are layered face to face, providing capacitive couplings between the pads. The report from Mizoguchi, et al (Non-patent document 3) introduces a system and a circuit for transmitting data through inductive couplings. Specifically, coils in the form of spiral inductors are formed in semiconductor interconnection areas on semiconductor chips at intervals of 100 μm, and the semiconductor chips are layered face to back, thereby providing inductive couplings.
If a plurality of semiconductor chips are layered using the technologies of through-hole interconnections, capacitive couplings, and inductive couplings, then it is possible to layer logic circuits and analog circuits as well as memory circuits mentioned in the examples above, for thereby achieving multifunctionality in addition to large storage capacity.
The through-hole interconnection technology needs the step of forming holes called through vias in the semiconductor substrate of a semiconductor chip for connecting the face and back of the semiconductor chip for data transmission and for forming an interconnection of an electrically conductive material such as metal in the through via, and the step of applying an insulating material to insulate the through interconnection from the semiconductor substrate. Therefore, the semiconductor fabrication process is complex or is highly costly and time-consuming. On the other hand, the capacitive coupling technology requires that the chips be layered face to face because capacitive couplings are formed between the facing pads on the surfaces of the chips. As a result, the chips that can be layered are limited to two layers, and there are limitations on the layering of three or more chips and on efforts to achieve multifunctionality and larger storage capacity.
Consequently, contactless interface technology based on inductive coupling is highly likely as a technology for layering three or more chips to contribute to making semiconductor devices with multifunctionality and larger storage capacity.
Contactless interface technology based on inductive coupling will briefly be described below. FIG. 1 is a block diagram of a structural example of a combined transmitting and receiving section according to the background art for sending and receiving data between chips. It is assumed that one bit of data is sent from one chip to another chip. It is also assumed that the polarity of data indicated by a signal voltage is “0” if the signal voltage has a ground potential and “1” if the signal voltage has a given potential which is determined as a voltage that is different from the ground potential.
As shown in FIG. 1, the transmitting section including chip 701 for transmitting data incorporates transmission coil 703 and transmitter 702. Transmitter 702 includes a variable-current-direction current source therein, and has a current direction variable depending on transmission data 704 input to a data input terminal. The current direction is positive when the current flows across transmission coil 703 from the left to the right in FIG. 1, and is negative when the current flows in the opposite direction. It is assumed hereinafter that if the coil is plotted horizontally, then the current direction is positive when the current flows from the left to the right and is negative when the current flows in the opposite direction, and if the coil is plotted vertically, then the current direction is positive when the current flows downwardly and is negative when the current flows in the opposite direction. The receiving section including chip 706 for receiving data incorporates reception coil 707 and receiver 708 connected across reception coil 707. Receiver 708 reads a current change developed in reception coil 707. Chip 701 and chip 706 are layered such that transmission coil 703 and reception coil 707 are in essentially superposed positions in a direction perpendicular to the chip planes.
When the polarity of transmission data 704 input to the data input terminal is “1”, the variable-current-direction current source supplies a current in the positive direction to transmission coil 703 in synchronism with transmission clock 705. When the current flows through transmission coil 703, transmission coil 703 generates a magnetic field due to the electromagnetic induction, causing reception coil 707 to induce a current. Receiver 708 reads a current change developed in reception coil 707. Similarly, when the polarity of transmission data 704 is “0”, reception coil 707 induces a current whose direction depends on the direction of the current flowing through transmission coil 703, and receiver 708 reads the induced current. Since the direction of the current induced in reception coil 707 is different depending on transmission data 704, reception data 709 output from the data output terminal corresponds to the polarity of transmission data 704. Accordingly, data can be transmitted between a plurality of layered chips even though interconnections are not provided between the chips for data transmission.
FIG. 2 shows a timing chart for signal transmission through the inductive coupling shown in FIG. 1, FIG. 3 shows a circuit diagram of an example of a transmission circuit, and FIG. 4 shows a circuit diagram of an example of a reception circuit.
According to the above signal transmission scheme, a current is supplied to a transmission coil fabricated on a chip to induce an electric signal in a reception coil that is fabricated on another chip which is separate from the chip with the transmission coil thereon, and the signal is observed, thereby transmitting the signal. In order to transmit a signal at a high rate and with a high quality such as a low error rate according to this transmission scheme, the signal induced in the reception coil has to be large enough to achieve a desired S/N ratio. The signal induced in the reception coil is proportional to the mutual inductance between the transmission and reception coils. The mutual inductance is proportional to the self-inductance of the reception coil, the self-inductance transmission coil, and the coupling coefficient between the coils. Since the coupling coefficient depends on the relative positions of the coils, the positions of the electromagnetic induction coils on the chips need to be adjusted with extremely high accuracy for realizing high-quality signal transmission.
If the coils are displaced out of position, then the mutual inductance decreases, resulting in a reduction in signal intensity. According to the above relevant art, it is very difficult to mount the chips while they are kept in highly accurate relative positions. Even if the chips can be mounted highly accurately, the packaging cost is increased. Furthermore, since the coil positions cannot be changed once the chips have been mounted in position, the transmission rate is limited, and the error rate cannot be sufficiently lowered.
The wire bonding which has been used in the layering SIP technology so far has made it possible to layer general-purpose chips because connecting positions can be changed to a certain extent. However, signal transmitting apparatus according to the background art which have used inductive couplings have been required to use chips having a dedicated design or chips having transmission and reception coils positionally aligned with each other for the reason that the transmission and reception coils have to be positionally aligned highly accurately with each other. Therefore, the manufacturing cost of the signal transmitting apparatus has been high.
Furthermore, device characteristic variations caused when semiconductor devices are manufactured make it impossible to sufficiently lower the error rate in signal transmission. For example, if there are characteristic variations between the transistors of the receiver, then they make the receiver behave as if an offset has been added to the input signal, tending to lead to an erroneous transmission of the signal.
Heretofore, the signal is received using only an induced current generated by the magnetic fluxes that pass through the reception coil which is mounted directly below the transmission coil. Accordingly, any magnetic fluxes that spread away from the magnetic fluxes that are directed directly below the transmission coil and pass through the reception coil are wasted. The current flowing through the transmission coil has been increased by an amount which is commensurate with the wasted magnetic fluxes, for transmitting the signal. As a consequence, the transmission power is increased, resulting in an increase in the consumption of power.    Patent document 1: JP4-196263A    Patent document 2: JP2002-26283A    Non-patent document 1: K. Takahashi et al., Japanese Journal of Applied Physics, 40, 3032 (2001)    Non-patent document 2: K. Kanda, et al., International Solid-State Circuits Conference, 2003    Non-patent document 3: D. Mizoguchi, et al., International Solid-State Circuits Conference, 2004